1. Field of the Invention
The present invention relates to an elastic integrated circuit including a simple elastic circuit to which data synchronized with the first clock is input, and from which data synchronized with the second clock is output.
2. Description of Related Art
A typical large scale integrated circuit such as a system LSI typically uses a clock tree circuit constituted by buffers, in order to supply a received clock to a logic circuit. The logic circuit processes data received thereby in the clock tree circuit using the clock supplied via the multiple staged buffer. In this case, if the number of the stages of buffer in the clock tree circuit is large and therefore the delay therein exceeds a half of the clock period, the phase relationship between the clock input to the clock tree circuit and the clock output therefrom is regarded as being uncertain in the circuit design. Thus, it is necessary to provide an elastic circuit in order to allow the data to be received and transmitted between the above clocks.
FIG. 6 shows a structure of an integrated circuit including a conventional elastic circuit.
As shown in FIG. 6, the elastic circuit 5 includes a memory circuit 51, a write address counter 52 and a read address counter 53.
To the write address counter 52, a clock is input via a clock terminal 21 before being input to a clock tree circuit 61. To a clock input C of the read address counter 53, a clock C0 to be used in a logic circuit 7, that is supplied via multiple stages of buffer in the clock tree circuit 60, is input. To the logic circuit 7 is input the clocks C0 and C1 via clock input terminals 41 and 42, respectively.
In a writing operation, a memory area in the memory circuit 51 into which input data is to be stored is specified by the count value of the write address counter 52, so that the input data input from an input terminal 1 is stored. In a reading operation, a memory region in the memory circuit 51 from which data is to be read is specified by the count value of the read address counter 53, so that the data stored in the specified memory area is read and is then input to the logic circuit 7 via an output terminal 3. Thus, data having a phase synchronized with the clocks C0 and C1 supplied from the multiple-stage buffers in the clock tree circuit 60 is input to the logic circuit 7.
The conventional circuit, however, has a problem where it is necessary to use a counter having a base number of four or more and a memory having four or more regions. FIG. 7 is a time chart in a case of using the conventional elastic circuit where a ternary (base three) counter is used. Referring to FIG. 7, the reason why the counter of the base number of four or more and the memory requires four or more regions in the circuit shown in FIG. 6 is described.
Herein, it is assumed that two count values are set to zero by an asynchronous reset signal having a one-bit width, which is externally input via the reset input terminal 22 in FIG. 6. In this case, the count value of the write address counter 52 is set to zero at a time tw1. This means that the reset signal is input between a time indicated by a solid line and a time indicated by a broken line (i.e., a period having about a two-bit width) in FIG. 7.
In this case, the count value of the read address counter 53 is also set to zero by the reset signal. However, the phase of the clock input to the read address counter 53 is not determined unlike the clock input to the write address counter 52. Thus, the read address counter 53 is reset at a certain rising between a time tr1 and a time tr2.
Consideration is then made of which count value of the read address counter #0 written in the memory circuit 51 is read, in a case where the write address count value is zero. #0 cannot be read out when the counter values of both the read address counter 53 and the write address counter 52 are zero. At a count value of the read address counter 53 of one, that is, when xe2x80x9ca read address counter {circle around (1)}xe2x80x9d is used, the count value of the read address counter 53 is set to zero at the time tr1 of the input clock. Thus, times of writing and reading operations are critical and therefore #0 cannot be read out confidently. At a count value of the read address counter 53 of two, that is, when the read address counter {circle around (2)}xe2x80x9d is used, next data is written into the memory circuit 51 at the time tr2 at which the count value of the writing address counter 52 is set to zero. Therefore, it is hard to read #0 confidently.
Therefore, the conventional circuit requires the counter having the base number of four or more in order to read #0 confidently when the read address counter 53 has the count value of two. (It should be noted that the capacity of the memory circuit 51 has to be increased in proportion to the base number of the counter.)
It is thus an object of the present invention to overcome the above issues of the conventional circuit and to provide an integrated circuit having a smaller area and a low power, to which data synchronized with the first clock is input and which outputs data synchronized with the second clock. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
According to an aspect of the present invention, an elastic integrated circuit to which data synchronized with a first clock is input and which outputs data synchronized with a second clock, is provided. The elastic integrated circuit includes: a base-(N+1) read address counter operating with the second clock to output a read address count value, where N is a natural number; a delay circuit to which the read address count value is input and which delays the read address count value by a predetermined time period to be output; a base-(N+1) write address counter to which the read address count value output from the delay circuit is loaded to be input and which operates with the first clock to output a write address count value; and a memory circuit into which input data is written by the write address count value and from which data written therein is read by the read address count value.
In one embodiment of the present invention, the delay circuit is a shift register including a plurality of flip-flops, in which each of the flip-flops operates with an operation clock having a phase delayed from that for another flip-flop connected thereafter.
In another embodiment of the present invention, the elastic circuit further includes a clock tree circuit in which S buffers are connected in series, where S is a natural number. Each of the S buffers has a delay smaller than one clock period. The first clock is input to the clock tree circuit that outputs the second clock having a total delay that is (Nxe2x88x921) clock periods or more but less than N clock periods, where N is a natural number.
In still another embodiment of the present invention, the delay circuit includes a plurality of flip-flops, and each of the flip-flops operates with an operation clock having a phase delayed from that for another flip-flop connected thereafter. The delay circuit operates by using the output of a predetermined one of the S buffers as an operation clock thereof.
This summary of the invention does not necessarily describe all necessary features so that the invention may also be a sub-combination of these described features.